(1) Field of the Invention
The present invention generally relates to a digital switching system, and more particularly to a sub-rate time switch which switches a digital multiplexed signal including a plurality of sub-rate signals in one time slot.
(2) Description of the Prior Art
A general switching method of a digital switching system handles 64 kbps signals. Recently, there has been considerable activity in the development of methods of compressing speech information in order to efficiently utilize digital transmission lines. In such compression methods, speech information is compressed to a sub-rate of, for example, 32 kbps, 16 kbps or 8 kbps, while a basic rate is 64 kbps. It is required that such compressed data be exchanged by a time switch which switches 64 kbps data.
Conventionally, speech information is converted to a 64 kbps PCM signal according to the CCITT recommendations. Particularly in Japan and the United States, the .mu.-law is employed to convert the speech information into a 64 kbps signal. In the 64 kbps signal, it is necessary to transmit 8 bits every 125 .mu.sec. For this reason, a 64 kbps switch system is generally employed.
Taking into account the recent activity in the research and development of speech compression schemes, the CCITT has issued the final recommendations about a 32 kbps ADPCM (Adaptive Differential PCM). The final recommendations have been practically used in some systems. Further, many companies have studied and proposed their own 16 kbps or 8 kbps compression schemes.
FIG. 1 shows a conventional digital exchange system which handles sub-rate signals, and FIG. 2 shows an input/output format of a codec LSI device shown in FIG. 1. Further, FIG. 3 shows the structure of a conventional 64 kbps time switch used in the system shown in FIG. 1, and FIG. 4 shows the structure of a conventional 32 kbps time switch used in the system shown in FIG. 1.
Referring to FIG. 1, the system includes a network NW including a path switch, subscriber lines 71 and 72, digital trunk (junction) lines 73 and 74 mutually connecting exchange systems, and a speech compression/decompression multiplexing unit 75 (hereafter simply referred to a multiplexing unit). In FIG. 1, subscribers (telephone sets) A and B are connected to the network NW via respective line circuits LC, and communicate with subscribers C and D via another exchange system (not shown), respectively. Digital signals, each having a basic rate of, for example, 64 kbps, are transferred between the subscribers A and B and the network NW. Signals transferred via each of the digital trunk lines 73 and 74 respectively include two sub-rate signals in one time slot in order to efficiently utilize the digital trunk lines 73 and 74. Each sub-rate signal has a sub-rate of 32 kbps.
The multiplexing unit 75 is provided for exchanging the basic-rate signals with the sub-rate signals. On the input side of the multiplexing unit 75, 64 kbps speech signals (8-bit digital signals) sent out from the subscribers A and B are assigned to time slots "0" and "1" by the network 70. Further, 32 kbps sub-rate signals (four-bit digital signals) sent from the subscribers C and D via the digital trunk line 74 are assigned to time slot "2" by the network 70. An input time slot signal (INPUT TS) 1 having a format shown in FIG. 1 is input to the multiplexing unit 75. For the sake of convenience, one frame consists of four time slots (or channels) "0" to "3", as shown in FIG. 1.
The input time slot signal (INPUT TS) 1 is changed to an input channel signal (INPUT CH) 2 by a primary time switch (SW0) 76 of the multiplexing unit 75. During this process, the signals, each having the basic rate, are output to a 32 kbps ADPCM codec (CODEC) 77 without any change, while the time slot "2" including two sub-rate signals is divided so that the two sub-rate signals are placed in separate channels (CH; the same as TS). The input channel signal 2 has a format shown in FIG. 2.
The input channel signal 2 is input to the codec 77, which encodes each of the basic-rate signals contained therein to a sub-rate code and decodes each of the sub-rate signals to a basic-rate code. Then, the codec 77 outputs an output channel signal (OUTPUT CH) 3 having a format shown in FIG. 2. The output channel signal 3 is input to a secondary time switch 78 of the multiplexing unit 75, at which the positions of time slots are changed by a random-write/sequential read procedure of the secondary time switch 78. Then, an output time slot signal (OUTPUT TS) 4 having a format shown in FIG. 1 is produced at the output side of the multiplexing unit 75. As shown, the format of the output time slot signal 4 includes, in time slot "0", the sub-rate signals from the subscribers A and B.
The primary time switch SW0 has the function of placing the plural (two) sub-rate signals which are present in one time slot of the input time slot signal into corresponding, plural a plurality of, (two) channels of the input channel signal, and the secondary time switch SW1 has the function of placing the plural (two) sub-rate signals which are present in the output channel signal into corresponding, plural (two) channels of one time slot of the output time slot signal.
A conventional 64 kbps time switch will now be described with reference to FIG. 3. In general, an input signal which is input to the 64 kbps time switch is a multiplexed signal obtained by multiplexing 8-bit signals, each being generated for every 125 .mu.s interval and has a frame which consists of 32 channels (time slots). The input signal is sequentially written into a speech path memory SPM (Speech Path Memory) of the 64 kbps time switch. During the write operation, write addresses are generated by a counter CT0. In FIG. 3, A0L-A2L are three low-order bits, which specify a write position (area) in which each bit in a specified input time slot is written, and A3L-A7L are five high-order bits of the counter CT0. The bits A3L-A7L specify a write position (area) corresponding to each input time slot number ("0"-"31"). The contents of the speech path memory SPM are read out therefrom at a time specified by software in the random read manner.
More specifically, a control memory CM has information about the time slots on the write side of the speech path memory SPM with respect to the time slot positions on the read side. The information about each time slot on the write side of the speech path memory SPM shows which position of the speech path memory SPM should be read. Such information can be written into the control memory CM under the software control of a controller (not shown). The time slot information on the write side is read from the control memory CM for each time slot on the read side thereof. The readout time slot information on the write side is input to the speech path memory SPM, from which data specified by the readout time slot information is read. During the above read operation, the position of each bit in each time slot is indicated by three-bit data generated and output by a counter CT1. In the above manner, data is read out from the speech path memory SPM in serial form.
In FIG. 3, each time slot, of all the time slots, has a basic-rate signal. In order to efficiently switch information having different frequency ranges, such as 64 kbps, 32 kbps, 16 kbps and 8 kbps, it is necessary for the controller (not shown) to know information about the frequency ranges.
FIG. 4 shows a conventional 32 kbps time switch capable of exchanging 64 kbps signals with 32 kbps signals in four-bit unit. The time switch shown in FIG. 4 writes the input signal in the speech path memory SPM in the sequential write manner while the write addresses are generated by the counter CT0. For example, when 32 kbps data is exchanged, the time slot number on the write side of the speech path memory SPM is placed at an address corresponding to the time slot position on the read side thereof. At this time, bit "2" is supplied, as bit information, to the speech path memory SPM. The bit "2" discriminates the first four bits "0"-"3", out of eight bits consisting of "0"-"7", from the second four bits "4"-"7". In the above manner, the time slot position of 32 kbps data (four bits) is exchanged.
When 64 kbps data (eight bits) is exchanged via the time switch shown in FIG. 4, two addresses of the control memory CM are needed because the time switch shown in FIG. 4 is designed to handle 32 kbps data (four bits). Thus, the read operation on the control memory CM must be carried out twice in order to handle 64 kbps data, and the software realizing the above-mentioned operation has a load which is twice that of the structure shown in FIG. 3.
The primary and secondary time switches SW0 and SW1 shown in FIG. 1 are formed with the time switches as shown in FIG. 4 in order to handle signals having different frequency ranges. Thus, the software of the multiplexing unit 75 has a large load.
Referring to FIG. 5, a speech path memory SPM0 and a control memory CM0 form the time switch 76 shown in FIG. 1, and a speech path memory SPM1 and a control memory CM1 form the time switch 78 shown in FIG. 1. The addresses of the control memories CM0 and CM1 which are directly handled by software are denoted by 0-7. Taking the control memory CM0 as an example, when 64 kbps data A is switched to the input channel from the input time slot, it is necessary to respectively write TS0,0 and TS0,1 in areas indicated by the addresses 0 and 1 of the control memory CM0 because A is placed in the areas of the addresses 0 and 1 of the speech path memory SPM0. Meanwhile, 32 kbps data `a` is placed in an area specified by address 4 of the speech path memory SPM0, and thus TS2,0 is written into an area specified by the address 4 of the control memory CM0.
When 64 kbps data is handled by a 16 kbps time switch, the address setting by software must be carried out four times. Similarly, when 64 kbps data is handled by an 8 kbps time switch, the address setting by software must be carried out eight times.